发明名称 |
WAFER-LEVEL PACKAGE HAVING MULTIPLE DIES ARRANGED IN SIDE-BY-SIDE FASHION AND ASSOCIATED YIELD IMPROVEMENT METHOD |
摘要 |
A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function. |
申请公布号 |
US2016240497(A1) |
申请公布日期 |
2016.08.18 |
申请号 |
US201615015110 |
申请日期 |
2016.02.03 |
申请人 |
MEDIATEK INC. |
发明人 |
Chen Yi-Hung;Liu Yuan-Chin |
分类号 |
H01L23/00;H01L25/00;H01L25/065 |
主分类号 |
H01L23/00 |
代理机构 |
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代理人 |
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主权项 |
1. A wafer-level package comprising:
a plurality of dies, comprising at least a first die and a second die, wherein the dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die; and a plurality of connection paths, configured to connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. |
地址 |
Hsin-Chu TW |