发明名称 INTEGRATED CIRCUIT PACKAGES WITH DUAL-SIDED STACKING STRUCTURE
摘要 An integrated circuit package may include a first integrated circuit die attached to a front surface of a second integrated circuit die. An intermediate layer made of a molding compound is formed to surround the second integrated circuit die in a “fan-out” arrangement while leaving a surface of the second integrated circuit die exposed. Accordingly, a group of via holes is then formed in the intermediate layer and filled with a conductive material. Such a configuration forms a dual-sided stacking structure. The stacking structure may also be applicable for package-on-package packages and fan-out wafer-level chip scale packages, in which the stacking structure is formed between two heterogeneous or homogeneous integrated circuit packages.
申请公布号 US2016240457(A1) 申请公布日期 2016.08.18
申请号 US201514625020 申请日期 2015.02.18
申请人 Altera Corporation 发明人 Lee Myung June
分类号 H01L23/48;H01L21/768;H01L21/56 主分类号 H01L23/48
代理机构 代理人
主权项 1. An integrated circuit package produced by a process comprising: providing a first integrated circuit die; providing a second integrated circuit die having opposing first and second surfaces and attaching the first integrated circuit die to the first surface of the second integrated circuit die; forming an intermediate layer on the first integrated circuit die and surrounding the second integrated circuit die; forming a plurality of via holes in the intermediate layer; and filling the plurality of via holes with a conductive material after forming the plurality of via holes.
地址 San Jose CA US