Apparatus for simplification of input signal

摘要

The present disclosure relates to an apparatus for simplification of input signal configured to simplify a process of microprocessor and to enhance a speed by transforming six input modes of 1-phase/2-input/1-multiplication mode, 1-phase/2-input/2-multiplication mode, CW/CCW mode, 2-phase/1-multiplication mode, 2-phase/2-multiplication mode and 2-phase/4-multiplication mode to a same shape according to types of encoder connected to a PLC high speed counter, and transmitting to the microprocessor, and by adding the six types of input modes to a logic gate circuit of a high speed counter input circuit.

主权项

1. An apparatus for simplification of input signal configured to input, to an MPU (Micro Processing Unit), an output of an input circuit at a PLC high speed counter module by converting the input to a single signal, the apparatus comprising:
a first detector configured to output a single pulse in response to a rising edge or a falling edge by detecting the rising edge or the falling edge of a reference signal, which is a reference of adding or deducting calculation in response to an operation mode of the high speed counter module; a second detector configured to detect, from an output of the first detector, a pulse of rising edge or falling edge configured to perform an actual adding or deducting calculation in response to an operation mode of the high speed counter module; and a switching unit configured to output an output of the second detector using the adding or deducting calculation.