Annotations to identify objects in design generated by high level synthesis (HLS)

摘要

Methods and systems provide creating and reporting of path annotations and renaming a state node using the path annotations for high level synthesis (HLS). In an embodiment, a method to annotate a state node includes identifying labels and pragmas specified in a high-level language input model for wait statements and function calls, and can also accommodate loops. In an embodiment, a method to display and/or report annotation information for a given state node includes displaying a state node name, an associated path annotation, and/or an associated hierarchical path. In an embodiment, a method to rename a state node based on a user-specified name includes using annotation information to locate a target state node and associating the target state node with the user-specified name or an automatically-created name based on the user-specified name. In an embodiment, a name specified for a state node can persist through successive runs of an HLS tool.

主权项

1. A processor-implemented method for an electronic design and verification tool to synthesize a behavioral description of a circuit into a structural description of the circuit, the method comprising:
using a processor:
facilitating generation of the structural description of the circuit by:
parsing the behavioral description of the circuit to identify a first text and/or a second text;defining a path annotation based on the identified first text and/or the identified second text; andannotating a state node with the path annotation; andgenerating the structural description of the circuit based on the facilitating.