| 发明名称 |
CACHE MEMORY, ERROR CORRECTION CIRCUITRY, AND PROCESSOR SYSTEM |
| 摘要 |
A cache memory includes cache memory circuitry that is accessible per cache line and a redundant-code storage that stores one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line and one or more numbers of second redundant codes to be used for error detection of a part of the cache line data. |
| 申请公布号 |
US2016378593(A1) |
申请公布日期 |
2016.12.29 |
| 申请号 |
US201615262241 |
申请日期 |
2016.09.12 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TAKEDA Susumu;NOGUCHI Hiroki;IKEGAMI Kazutaka;FUJITA Shinobu |
| 分类号 |
G06F11/10;G06F12/0811;G06F12/0893;G06F3/06;H03M13/29 |
主分类号 |
G06F11/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A cache memory comprising:
cache memory circuitry that is accessible per cache line; and a redundant-code storage that stores one or more numbers of first redundant codes to be used for error correction of cache line data stored in the cache memory circuitry per cache line and one or more numbers of second redundant codes to be used for error detection of a part of the cache line data. |
| 地址 |
Tokyo JP |
