发明名称 |
APPARATUS AND METHOD FOR EFFICIENT CALL/RETURN EMULATION USING A DUAL RETURN STACK BUFFER |
摘要 |
An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. For example, one embodiment of a processor comprises: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB. |
申请公布号 |
US2016378466(A1) |
申请公布日期 |
2016.12.29 |
申请号 |
US201514751052 |
申请日期 |
2015.06.25 |
申请人 |
XEKALAKIS POLYCHRONIS;AGRON JASON M. |
发明人 |
XEKALAKIS POLYCHRONIS;AGRON JASON M. |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
1. A processor comprising:
a dual return stack buffer (RSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB. |
地址 |
San Jose CA US |