| 摘要 |
PURPOSE:To reduce a planar area required for connecting an MISFET for switching and a capacitance element for storing information by removing one part of a dielectric film in the upper section of the side wall of a small hole in a self-alignment manner and forming a connecting hole connected to one semiconductor region in the MISFET. CONSTITUTION:A field insulating film 3, a p-type channel stopper region 4 and a mask 16 are shaped to the main surface of a semiconductor region 2 between memory cell forming regions, and a small hole 5 is formed. A dielectric film 6 is shaped onto each surface of a semiconductor substrate 1 and the semiconductor region 2 in the small hole 5, and each of a mask 7A and a mask 17 is laminated to the upper section of the film 6 in succession. The mask 17 formed onto the plane of a section except the small hole 5 is removed partially, and the mask 7A is etched until the upper section of the side wall of the small hole 5 is gotten rid of. One part of the dielectric film 6 is taken off by employing the mask 7A to shape a connecting hole 6A, and PSG films 16C in the mask 17 and the mask 16 are removed. An electrode 7 is formed into the small hole 5 so as to be brought into contact with the semiconductor region 2 through the connecting hole 6A. |
