发明名称 |
Semiconductor memory device for providing address access time and data access time at a high speed |
摘要 |
A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.
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申请公布号 |
US2002001240(A1) |
申请公布日期 |
2002.01.03 |
申请号 |
US20010867811 |
申请日期 |
2001.05.30 |
申请人 |
RYU JE-HUN;HAN JONG-HEE |
发明人 |
RYU JE-HUN;HAN JONG-HEE |
分类号 |
G11C11/407;G06F1/12;G11C7/22;G11C8/18;G11C11/4076;G11C11/408;H03L7/081;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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