SOURCE-SYNCHRONOUS RECEIVER USING EDGE-DETECTION CLOCK RECOVERY

摘要

A source-synchronous clocking signal is sampled by an edge sampler triggered by a phase-adjusted version of the clocking signal. The output of the edge sampler is used as a phase-error indicator for a filtered feedback loop that aligns the phase-adjusted clocking signal to minimize, on average, the difference between the received source-synchronous clocking signal and the phase-adjusted version of the clocking signal minus the setup time of the sampler. This forms a delay-locked loop configuration. The phase adjustment information used to produce the aligned phase-adjusted clocking signal is then to produce a receiver clocking signal that is used to sample the source-synchronous data signal.

主权项

1. A receiver circuit, comprising:
a first sampler circuit to resolve a data signal in response to a first timing reference signal received from a phase-alignment circuit; a second sampler circuit to resolve a timing reference signal in response to a second timing reference signal from the phase-alignment circuit and to output a phase indicator; and, the phase-alignment circuit to produce, based on the timing reference signal and the phase indicator, the first timing reference signal and the second timing reference signal.