发明名称 |
Level shifter, DC-DC converter, and level shift method |
摘要 |
A level shifter includes: a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity type which are cascode-coupled to each other, configured to transmit a first input signal; a second cascode portion, including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are cascode-coupled to each other, configured to transmit a second input signal; a latch portion configured to retain a first output signal and a second output signal obtained by changing, based on a first voltage obtained by boosting a power supply voltage, potential levels of the first input signal and the second input signal; and a potential-difference suppression circuit, coupled in parallel to the first cascode portion, configured to control a potential difference between source and drain of each of the first transistor and the second transistor. |
申请公布号 |
US9438239(B2) |
申请公布日期 |
2016.09.06 |
申请号 |
US201414455626 |
申请日期 |
2014.08.08 |
申请人 |
FUJITSU LIMITED |
发明人 |
Gao Hong |
分类号 |
H02M1/08;H03K19/0185;H02M3/158;H02M1/00 |
主分类号 |
H02M1/08 |
代理机构 |
Arent Fox LLP |
代理人 |
Arent Fox LLP |
主权项 |
1. A level shifter comprising:
a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity type which are cascode-coupled to each other, configured to transmit a first input signal; a second cascode portion, including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are cascode-coupled to each other, configured to transmit a second input signal which is in a complementary relation with the first input signal; a latch portion configured to retain a first output signal and a second output signal obtained by changing, based on a first voltage obtained by boosting a power supply voltage, potential levels of the first input signal and the second input signal; and a potential-difference suppression circuit, coupled in parallel to the first cascode portion, configured to control a potential difference between a source and a drain of each of the first transistor and the second transistor, wherein a drain of the first transistor is coupled to a drain of the second transistor at a first node, and the potential-difference suppression circuit includes a first protection element and a second protection element having one terminal coupled to one terminal of the first protection element at a second node which is coupled to the first node. |
地址 |
Kawasaki JP |