Low area full adder with shared transistors

摘要

A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum.

主权项

1. A full adder comprising:
an exclusive NOR logic circuit configured to receive a first input and a second input; a first inverter configured to receive an output of the exclusive NOR logic circuit and configured to generate an exclusive OR output; a carry generation circuit configured to receive the output of the exclusive NOR logic circuit, the exclusive OR output and a third input, the carry generation circuit configured to generate an inverted carry; and a sum generation circuit configured to receive the output of the exclusive NOR logic circuit, the exclusive OR output and the third input, the sum generation circuit configured to generate an inverted sum.