| 摘要 |
PROBLEM TO BE SOLVED: To provide a phase synchronization circuit which reduces frequency fluctuation to 1ppb or below, shortens pull-in time and achieves stable and highly precise time synchronization.SOLUTION: A phase synchronization circuit A includes: phase monitoring means A1 for determining presence or absence of packet jitter of an inputted time signal; jitter removal means A2 for removing the packet jitter from the time signal; and wandering removal means A3 for removing packet wandering from the time signal. The circuit also includes signal switching means A4 which allows the time signal to pass through the jitter removal means and the wandering removal means when the packet jitter is determined to exist in the inputted time signal, and allows the time signal to directly pass through the wandering removal means when the packet jitter is determined not to exist in the inputted time signal. |
