发明名称 |
MEMORY CONTROLLER AND COMPUTING APPARATUS THE SAME |
摘要 |
A memory controller and a computing device including the same are provided to shorten a booting time of a system by detecting a phase value within two cycles of a reference clock. A phase detector(100) delays a reference clock as much as a delay value and outputs the delayed reference clock. A delay controller(200) adjusts a phase value to be output depending on accordance by comparing the detected phase value with a preset phase value. A delay processor(300) delays the reference clock as much as the delay value set by the phase value received from the delay controller. The phase detector includes a ring oscillator generating/outputting an oscillation clock, an oscillation clock counting the output oscillation clock, a sampler receiving the reference clock and sampling the number of oscillation clocks counted for one cycle of the reference clock, and a phase value output unit outputting the number of sampled oscillation clocks as the phase value of the reference clock.
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申请公布号 |
KR20080082450(A) |
申请公布日期 |
2008.09.11 |
申请号 |
KR20080016779 |
申请日期 |
2008.02.25 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KOO, TAE WOON;LEE, YOON TAE;KIM, KYU SUNG;PARK, YOUNG JIN |
分类号 |
G06F12/00;G06F1/04 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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