发明名称 |
MULTIPLE PROCESSOR ARCHITECTURE WITH FLEXIBLE EXTERNAL INPUT/OUTPUT INTERFACE |
摘要 |
A multiple processor architecture with flexible external input/output interface is provided. In one embodiment, an open flexible processor architecture avionics device comprises: a multiple processor architecture having a primary processor, a secondary processor, a random access memory (RAM) coupled to at least the secondary processor, and a shared memory coupled to the primary and secondary processor; and a flexible input/output (I/O) interface coupled to the multiple processor architecture, wherein the flexible I/O interface provides I/O access to the primary processor using a fixed I/O protocol, and provides I/O access to the secondary processor using at least one re-configurable I/O protocol; wherein the primary processor is dedicated to executing embedded software for implementing a primary base functionality, the primary processor has read and write access to the shared memory, and the primary processor is not reprogrammable; and wherein the secondary processor has read-only access to the shared memory and is programmable. |
申请公布号 |
US2016239455(A1) |
申请公布日期 |
2016.08.18 |
申请号 |
US201514622571 |
申请日期 |
2015.02.13 |
申请人 |
Honeywell International Inc. |
发明人 |
Merritt Ross;Matthews Christopher Jay;Van-Cao Dang Tu;Lund Christopher A.;Buck Timothy Merrill |
分类号 |
G06F13/42;G06F12/02;G06F13/30;G11C7/10;G06F13/16 |
主分类号 |
G06F13/42 |
代理机构 |
|
代理人 |
|
主权项 |
1. An open flexible processor architecture avionics device, the device comprising:
a multiple processor architecture having at least a primary processor, at least a secondary processor, a random access memory (RAM) coupled to at least the secondary processor, and a shared memory coupled to the primary processor and the secondary processor; and a flexible input/output (I/O) interface coupled to the multiple processor architecture, wherein the flexible I/O interface provides I/O access to the primary processor using a fixed I/O protocol, and provides I/O access to the secondary processor using at least one re-configurable I/O protocol; wherein the primary processor is dedicated to executing embedded software for implementing a primary base functionality, the primary processor has read and write access to the shared memory, and the primary processor is not reprogrammable; and wherein the secondary processor has read-only access to the shared memory and is programmable. |
地址 |
Morristown NJ US |