Patterning approach to reduce via to via minimum spacing

摘要

A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches.

主权项

1. A method of forming a semiconductor device, the method comprising:
forming a first mask layer over an underlying layer; forming a first line opening in the first mask layer using a first patterning process; after forming the first line opening, forming a second line opening in the first mask layer using a second patterning process; forming a second mask layer over the first mask layer, the second mask layer having a via opening, the via opening exposing portions of the first line opening and the second line opening; etching vias in the underlying layer using the first mask layer and the second mask layer as mask; removing the second mask layer; and after removing the second mask layer, simultaneously etching to extend the vias and to form lines in the underlying layer using the first mask layer as a mask.