| 摘要 |
The memory stage (Ax) consists of several logic gating elements (3, 5, 7, 8), two memory cells (FFA, FFB) which are antivalent in their signal state and a gating means (4) which checks the memory outputs (QA, QB) for the antivalent signal state. If these signal states are equivalent, the memory cells (FFA, FFB) are immediately aligned into the uncritical and predetermined signal state, as a result of which the memory stage (Ax) assumes the preferred security-primary position. In the case of an error, an integrated or external ERROR flip flop (6) is set and provides an error message for a security-efficacious response of the microprocessor. <IMAGE> |
