发明名称 |
Bit line precharge circuit |
摘要 |
An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.
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申请公布号 |
US5754487(A) |
申请公布日期 |
1998.05.19 |
申请号 |
US19960749277 |
申请日期 |
1996.11.13 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM, DU-EUNG;KWAK, CHOONG-KEUN;SUH, YOUNG-HO;BYUN, HYUN-GEUN |
分类号 |
G11C11/41;G11C7/12;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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