| 摘要 |
A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.
|
