发明名称 CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME
摘要 A CGC includes an enable module (302) and a latch module (306). The enable module (302) has an enable module input and an enable module output. The latch module (306) has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module (306) is configured to enable and to disable the clock (clk_in) via the latch module output based on the enable module input. The latch module (306) includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output, the internal enable node and the clock.
申请公布号 WO2016114892(A3) 申请公布日期 2016.09.01
申请号 WO2015US66116 申请日期 2015.12.16
申请人 QUALCOMM INCORPORATED 发明人 RASOULI, Seid Hadi;DILLEN, Steven James;DATTA, Animesh
分类号 H03K19/00 主分类号 H03K19/00
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