Structure, method and system for complementary strain fill for integrated circuit chips

摘要

A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.

主权项

1. A computer system comprising:
a processor; and a computer-readable memory device coupled to communicate with said processor, said memory device containing instructions that, when executed by the processor, implement a method for complementary strain fill for integrated circuit chips by: generating an integrated circuit chip design for an integrated circuit chip; generating a tensile layer etch mask design for an etch mask used to etch a tensile stressed dielectric layer as specified in said integrated circuit chip design; generating a second mask design for an etch mask used to etch a compressive stressed dielectric layer as specified in said integrated circuit chip design; identifying active regions of an integrated circuit having a plurality of n-channel field effect transistors (NFETs) and a plurality of p-channel field effect transistors (PFETs); identifying inactive regions of said integrated circuit design not containing NFETs or PFETs; placing fill shapes in said layer etch mask design and in said compressive layer etch mask design, said fill shapes placed only in respective regions of said tensile layer etch mask design and said compressive layer etch mask design corresponding to said inactive regions, and said fill shapes defining areas of said tensile stressed dielectric layer to be removed from said integrated circuit chip fabricated based on said tensile layer etch mask design and areas of said compressive stressed dielectric layer to be removed from said integrated circuit chip fabricated based on said compressive layer etch mask design; and storing said tensile and compressive etch mask designs on a computer readable device.