主权项 |
1. An integrated circuit comprising:
A. functional circuits that include a first bond pad and a second bond pad, the functional circuits including first level circuitry, second level circuitry, and third level circuitry; B. first test circuitry including:
i. first parallel scan path circuits, each of the first parallel scan path circuits having stimulus outputs connected to the first level circuitry, response inputs connected to the first level circuitry, a serial input and a serial output;ii. first distributor circuits having a serial input connected to the first bond pad, a serial output, and parallel outputs, each parallel output being connected to an input of a first parallel scan path circuit; andiii. first collector circuits having a serial output connected to the second bond pad, a serial input, and parallel inputs, each parallel input being connected to an output of a first parallel scan path circuit; C. second test circuitry including:
i. second parallel scan path circuits, each of the second parallel scan path circuits having stimulus outputs connected to the second level circuitry, response inputs connected to the second level circuitry, a serial input and a serial output;ii. second distributor circuits having a serial input connected to the output of the first distributor circuits, a serial output, and parallel outputs, each parallel output being connected to an input of a second parallel scan path circuit; andiii. second collector circuits having a serial output connected to the serial input of the first collector circuits, a serial input, and parallel inputs, each parallel input being connected to an output of a second parallel scan path circuit; and D. third test circuitry including:
i. third parallel scan path circuits, each of the third parallel scan path circuits having stimulus outputs connected to the third level circuitry, response inputs connected to the third level circuitry, a serial input and a serial output;ii. third distributor circuits having a serial input connected to the output of the second distributor circuits, a serial output, and parallel outputs, each parallel output being connected to an input of a third parallel scan path circuit; andiii. third collector circuits having a serial output connected to the serial input of the second collector circuits, a serial input, and parallel inputs, each parallel input being connected to an output of a third parallel scan path circuit. |