Integration method for a vertical nanowire transistor

摘要

The present invention discloses a method for integrating a vertical nanowire transistor and belongs to a field of field effect transistor logic device in a CMOS ultra-large scale integrated circuit (ULSI). The method realizes the integration of the vertical-nanowire transistor by combining selective epitaxy and replacement gate on sidewall. In comparison with an existing method for forming a vertical nanowire channel by etching, a size and shape of a cross section of a device channel can be accurately controlled, a consistency of device characteristic can be improved, and an etching damage during the forming of a channel in the existing method can be avoided, thereby the device performance can be improved.

主权项

1. An integration method for a vertical nanowire transistor, comprising:
A) providing a semiconductor substrate, and forming an isolation between devices; B) forming heavily-doped lower active regions of the devices; C) depositing a dummy gate stack layer, which specifically comprises the steps of:
C1) depositing a medium layer as a first source-drain extension region (SDE) mask layer, of which a thickness defines a length of a source-drain extension region (SDE) of the devices;C2) depositing a medium layer as a dummy gate layer, of which a thickness defines a channel length Lg of the devices;C3) depositing a medium layer as a second SDE mask layer, of which a thickness defines the length of a source-drain extension region (SDE) of the devices; D) forming channels by selective epitaxy, which specifically comprises the steps of:
D1) defining epitaxial windows of the channels via lithography, of which sizes and shapes determine sizes and shapes of cross sections of the channels of the devices;D2) forming the epitaxial windows of the channels via anisotropic etching, through the bottom of which the heavily-doped lower active regions of the devices are exposed;D3) forming the channels of the devices via epitaxy, and removing an epitaxial channel material that exceeds an upper surface of the second SDE mask layer via CMP, to realize planarization; E) forming heavily-doped upper active regions of the devices by selective epitaxy, which specifically comprises the steps of:
E1) depositing a medium layer as a hard mask, and exposing channels of NMOSs via lithography and anisotropic etching;E2) forming heavily-doped upper active regions of the NMOSs via in-situ doped epitaxy;E3) removing the hard mask;E4) depositing a medium layer as a hard mask, and exposing channels of a PMOSs via lithography and anisotropic etching;E5) forming a heavily-doped upper active region of the PMOS via in-situ doped epitaxy;E6) removing the hard mask;E7) activating source-drain impurities via an annealing process, and diffusing the source-drain impurities into the SDE region to form an LDD; F) removing the dummy gate layer, depositing and forming a gate electrode and high K material, which specifically comprises the steps of:
F1) depositing a medium layer as a top mask layer;F2) defining the gate electrode via lithography;F3) exposing an upper surface of the first SDE mask layer via anisotropic etching;F4) removing the whole dummy gate layer via isotropic etching;F5) sequentially depositing a high-K medium material as gate oxide and a metal gate material;F6) removing the high K and gate material that is not covered by the top mask layer via anisotropic etching, to expose the upper surface of the first SDE mask layer; H) forming a metal contact on each terminal of the devices, which specifically comprises the steps of:
H1) depositing a medium layer as an inter-layer isolation, and realizing planarization via CMP;H2) forming a contact hole on each terminal of the devices via lithography and anisotropic etching;H3) filling each contact hole with a metal;H4) realizing the separation of conductive layers between devices by performing CMP on the metal, to realize an effect of device isolation; I) accomplishing device integration subsequently by a backend process.