Voltage switch circuit

摘要

A voltage switch circuit is connected to a memory cell of a non-volatile memory. When the non-volatile memory is in a program mode and the memory cell is a selected memory cell, two output terminals provide a high voltage. When the non-volatile memory is in the program mode and the memory cell is a non-selected memory cell, the two output terminals provide a medium voltage and a ground voltage. When the non-volatile memory is in an erase mode and the memory cell is the selected memory cell, the two output terminals provide the high voltage and the ground voltage. When the non-volatile memory is in the erase mode and the memory cell is the non-selected memory cell, the two output terminals provide the ground voltage. When the non-volatile memory is in a read mode, the two output terminals provide a read voltage.

主权项

1. A voltage switch circuit connected to a memory cell of a non-volatile memory, the voltage switch circuit comprising:
a first transistor, wherein a source terminal of the first transistor is connected to a first voltage source, and a gate terminal of the first transistor is connected to a node a1; a second transistor, wherein a source terminal of the second transistor is connected to the first voltage source, and a gate terminal of the second transistor is connected to a node b1; a third transistor, wherein a source terminal of the third transistor is connected to a drain terminal of the first transistor, a gate terminal of the third transistor receives an enabling signal, and a drain terminal of the third transistor is connected to a node a2; a fourth transistor, wherein a source terminal of the fourth transistor is connected to a drain terminal of the second transistor, a gate terminal of the fourth transistor receives the enabling signal, and a drain terminal of the fourth transistor is connected to a node b2; a fifth transistor, wherein a source terminal of the fifth transistor is connected to the node a2, a gate terminal of the fifth transistor is connected to a second voltage source, and a drain terminal of the fifth transistor is connected to a first output terminal; a sixth transistor, wherein a source terminal of the sixth transistor is connected to the node b2, a gate terminal of the sixth transistor is connected to a third voltage source, and a drain terminal of the sixth transistor is connected to a second output terminal; a seventh transistor, wherein a source terminal of the seventh transistor is connected to a fourth voltage source, a gate terminal of the seventh transistor is connected to the second output terminal, and a drain terminal of the seventh transistor is connected to the node a2; a first control circuit connected to the node a1, the node b1 and the node a2; and a second control circuit connected to the first output terminal and the second output terminal, wherein in a program mode and an erase mode of the non-volatile memory, the first voltage source provides a high voltage, the second voltage source provides a medium voltage or a ground voltage, the third voltage source provides a control voltage, and the fourth voltage source provides the medium voltage, wherein in a read mode of the non-volatile memory, all of the first voltage source, the second voltage source and the third voltage source provide a high logic level voltage, and the fourth voltage source provides the ground voltage, wherein the high voltage is higher than the medium voltage, the medium voltage is higher than the high logic level voltage, and the control voltage is in a range between the medium voltage and the high voltage.