| 主权项 |
1. An asynchronous floating-point adder comprising:
a front end component receiving a first input and second input, the first and second input being described in exponent/significand form; said front end analyzing the first and second input and obtaining a difference between an exponent of the first input and an exponent of the second input; said difference comprising a difference in exponents; an alignment shift component receiving the difference in exponents; the alignment shift component aligning significands of the first and second inputs when exponents are different; aligned significands being adder inputs; an adder component receiving the adder inputs from said alignment shift component; a leading one predictor (LOP)/decoder component receiving adder inputs from said alignment shift component; a left shift/exponent adjustment determination component receiving an output of said adder component and an output of said leading one predictor/decoder component; a right shift/exponent adjustment determination component receiving an output of said adder component; and a left-right selection component; an output of said left-right selection component being utilized to provide an output of the asynchronous floating-point adder; said front end component, said shifter component, said adder component, said leading one predictor (LOP)/decoder component, said left shift/exponent adjustment determination component, said right shift/exponent adjustment determination component and said left-right selection component utilizing quasi-delay insensitive (QDI) asynchronous circuits; said front end component, said alignment shift component, said adder component, said leading one predictor (LOP)/decoder component, said left shift/exponent adjustment determination component, said right shift/exponent adjustment determination component and said left-right selection component being asynchronously pipelined; asynchronously pipelining enabling optimization of operand. |
