| 摘要 |
PURPOSE:To decrease a wiring delay time by using a long wiring without impairing the performance of a basic gate and layout property by arranging low-current gate cells and high-current gate cells on a gate array substrate, and using the high-current gates when the long wiring is formed. CONSTITUTION:Many gate cells are arranged on a gate part 14 of a chip 11 in a matrix pattern. Cells 15 indicated by shaded parts are high-current gate cells exclusive for long wirings. Other cells 16 are low-current gate cells. The high-current gate 15 has a constitution wherein a current flowing through a switching transistor and an emitter follower transistor is twice a current flowing through a transistor for the low-current gate. Therefore, when the high-current gate is used when the wiring is long, a wiring delay time can be made quicker than the time when the low current cell is used. Thus, the wiring delay time can be decreased by using the high-current gate 15 when a long wiring 17 is formed. For a wiring 18 with a short distance between the gates, the low-current gates 16 are used. |
