| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology for speeding up a semiconductor integrated circuit device which has a MISFET formed on an SOI substrate and improving reliability. SOLUTION: A groove, which is surrounded by a side wall spacer 11 and whose depth (d) is about 90-100 nm is formed on a polycrystalline silicon film 6, constituting the gate electrode of a MISFET. Silicons 13a and 13b with a thickness of about 100 nm are stacked on the surface of the exposed thin-film silicon layer 3. Thereafter, a titanium silicide layer is formed on the surfaces of the silicons 13a and 13b through self-matching.
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