发明名称 |
Method for designing diodes |
摘要 |
A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event. |
申请公布号 |
US9418197(B1) |
申请公布日期 |
2016.08.16 |
申请号 |
US201514612071 |
申请日期 |
2015.02.02 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Farbiz Farzan;Appaswamy Aravind C.;Salman Akram A.;Boselli Gianluca |
分类号 |
G06F9/455;G06F17/50 |
主分类号 |
G06F9/455 |
代理机构 |
|
代理人 |
Chan Daniel;Cimino Frank D. |
主权项 |
1. A method of designing a circuit for suppressing electrostatic discharge, the method comprising:
generating a first layout including a first diode; calculating a first calculated voltage overshoot of the first diode based on the first layout and first variables of: a length of an N region of the first diode; current density during an ESD event; electron charge; hole mobility; electron mobility; a doping concentration of the first diode; and a rise time of the ESD event; generating a second layout including a second diode; calculating a second calculated voltage overshoot of the second diode based on the second layout and second variables of: a length of an N region of the second diode; the current density during the ESD event; the electron charge; the hole mobility; the electron mobility; a doping concentration of the second diode; and the rise time of the ESD event, wherein an anode of the first diode is coupled to a cathode of the second diode; and determining whether the first and second calculated voltage overshoots meet a predetermined threshold. |
地址 |
Dallas TX US |