Automatically placed-and-routed ADPLL with PWM-based DCO resolution enhancement

摘要

An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (fREF) at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to multiple tunable delay elements; receiving at the multiple tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit; providing an PLL output (fDCO) to the TDC at least partially based on the first signal input; and generating a phase error output (ΦERR) based on the reference signal (fREF) and the PLL output (fDCO), wherein the phase error output (ΦERR) is provided as feedback to the controller to control the PLL output (fDCO).

主权项

1. A method of controlling a phase-locked loop (PLL) output using an all digital phase-locked loop (ADPLL), comprising the steps of:
receiving a reference signal at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to a plurality of tunable delay elements; receiving at the plurality of tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit; providing an PLL output to the TDC at least partially based on the first signal input; and generating a phase error output based on the reference signal and the PLL output, wherein the phase error output is provided as feedback to the controller to control the PLL output.