| 摘要 |
PURPOSE:To enable failure of a signal within a logic circuit whose failure cannot be detected easily by an external output terminal to be detected easily. CONSTITUTION:A synchronous order circuit is provided with an exclusive OR circuit 7 which inputs an execution control signal 5 which selects and controls three execution modes of a normal mode, a shift mode, and a test mode and an output of a F/F2 at a previous stage on a scan path and a signal 8 whose failure cannot be detected easily by an external output terminal 9 which is selected properly. Therefore, when the test mode is specified by the execution control signal 5, an output of the exclusive OR circuit 7 is selected as an input of the F/F for shift operation and an output of the F/F at the final stage of scan path is tested, thus enabling a failure of the signal 8 to be detected with an extremely high probability. |
