发明名称 |
MICROINSTRUCTION ADDRESSING IN HIGH-SPEED CPU |
摘要 |
MICROINSTRUCTION ADDRESSING IN HIGH-SPEED CPU A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An unconditional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the microinstruction does not prevent completion of the stack operation in one machine cycle.
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申请公布号 |
CA1323939(C) |
申请公布日期 |
1993.11.02 |
申请号 |
CA19890606105 |
申请日期 |
1989.07.19 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
GRUNDMANN, WILLIAM J.;MADDEN, WILLIAM C.;UHLER, GEORGE M. |
分类号 |
G06F7/78;G06F9/22;G06F9/26;G06F9/30;(IPC1-7):G06F9/26 |
主分类号 |
G06F7/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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