发明名称 IC-TESTING DEVICE
摘要 PROBLEM TO BE SOLVED: To test a mixed IC where an AD converter or a DA converter is mounted by connecting unused fail analysis memories in cascade for composing a mass storage memory, and by storing AD conversion data where AD or DA conversion output is subjected to AD conversion again into the mass storage memory. SOLUTION: Unused fail analysis memories 118A-118N are utilized in cascade for storing bit data being outputted to each output pin of an AD converter, and the need for using a mass storage memory is eliminated. The fail analysis memory 118A is selected by a selector 150, and, for example, the least significant bit data being outputted to an output terminal ADOUT1 of the AD converter being mounted to an IC 119 to be tested is stored into the fail analysis memory 118A. An overflow signal FULL being outputted by the fail analysis memory 118A is inputted into a select controller 151 through an OR gate OR, and the selector 150 is controlled by the select controller 151, thus changing to a state for selecting the fail analysis memory 118B.
申请公布号 JP2000180516(A) 申请公布日期 2000.06.30
申请号 JP19980354814 申请日期 1998.12.14
申请人 ADVANTEST CORP 发明人 ITO MASAYUKI
分类号 G01R31/316;G01R31/28;H03M1/10;(IPC1-7):G01R31/316 主分类号 G01R31/316
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