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发明名称
DUAL-LOOP PLL CIRCUIT AND CHROMINANCE DEMODULATION CIRCUIT USING THE SAME
摘要
申请公布号
KR20010033521(A)
申请公布日期
2001.04.25
申请号
KR1020007007023
申请日期
2000.06.22
申请人
发明人
分类号
H04N9/44
主分类号
H04N9/44
代理机构
代理人
主权项
地址
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