| 摘要 |
<p>For example, multi-cycle path information is extracted from a logic synthesis restriction (S101) and a multi-cycle path verification property indicating a verification content is generated (S102). After this, according to a network list of a gate level generated separately by the logic synthesis based on an RTL circuit description by using a logic synthesis tool, a formal verification is performed and the multi-cycle path verification property is reference and executed so as to verify the multi-cycle path (S103). This can surely and easily verify the validity of the multi-cycle path inforamtmion.</p> |
