RECONFIGURABLE INTERCONNECT ELEMENT WITH LOCAL LOOKUP TABLES SHARED BY MULTIPLE PACKET PROCESSING ENGINES

摘要

The invention describes the design of an interconnect element in a programmable network processor/system on-chip having multiple packet processing engines. The on-chip interconnection network for a large number of processing engines on a system can be built from an array of the proposed interconnect elements. Each interconnect element also includes local network lookup tables which allows its attached processing engines to perform lookups locally. These local lookups are much faster than the lookups to a remote search engine, which is shared by all processing engines in the entire system. Local lookup tables in each interconnect element are built from a pool of memory tiles. Each lookup table can be shared by multiple processing engines attached to the interconnect element; and each of these processing engines can perform lookups on different lookup tables in run-time.

主权项

1. An interconnect element in a network-processing system on chip, comprising:
a plurality of primary input ports and a plurality of primary output ports configured to connect with other interconnect elements; a plurality of PE ports configured to connect with a plurality of local processing engines (PEs); a routing kernel configured to route a plurality of incoming packets; a pool of shared memory tiles configured to form one or more lookup tables utilized by its local PEs.