| 摘要 |
Techniques for providing transformer-based CMOS oscillators capable of operation with low voltage power supplies. In an exemplary embodiment, an LC tank is provided at the drains of a transistor pair, and the inductance of the LC tank is mutually magnetically coupled to an inductance between the gates of the transistor pair. A separate complementary transistor pair is also coupled to the LC tank. A further exemplary embodiment provides an LC tank at the gates of a transistor pair, as well as for three-way coupling amongst a tank inductance, an inductance between the gates of the transistor pair, and an inductance between the gates of a complementary transistor pair. |
| 主权项 |
1. An apparatus for generating signals having a controlled oscillation frequency at a pair of output nodes, the apparatus comprising:
a first transistor and a second transistor, wherein a drain of the first transistor is coupled to a first node of the pair of output nodes and a drain of the second transistor is coupled to a second node of the pair of output nodes; a first inductor coupled to a gate of the first transistor and a gate of the second transistor; a differential amplifier, wherein an inverting input of the differential amplifier is coupled to the second node of the pair of output nodes, a non-inverting input of the differential amplifier is coupled to a reference voltage, and an output of the differential amplifier is coupled to the first inductor; a second inductor coupled to the first node of the pair of output nodes and the second node of the pair of output nodes, wherein the second inductor is magnetically coupled to the first inductor, a capacitor coupled to the first node of the pair of output nodes and the second node of the pair of output nodes; a third transistor and a fourth transistor, wherein a drain of the third transistor is coupled to the first node of the pair of output nodes and a drain of the fourth transistor is coupled to the second node of the pair of output nodes; and a third inductor coupled to a gate of the third transistor and a gate of the fourth transistor, wherein the third inductor is magnetically coupled to the second inductor, and wherein the third inductor is tapped with a bias voltage. |
