发明名称 Semiconductor device having mid-gap work function metal gate electrode
摘要 Provided is a semiconductor device having mid-gap work function metal gate electrodes. The semiconductor device includes a plurality of gate patterns, and the gate patterns have different gate electrode metals from each other or different gate electrode metal thicknesses from each other.
申请公布号 US9461132(B2) 申请公布日期 2016.10.04
申请号 US201414511193 申请日期 2014.10.10
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Cheon Keon-Yong;Kim Il-Ryong;Kim Dong-Won
分类号 H01L21/70;H01L29/423;H01L29/49;H01L21/8238;H01L27/092;H01L29/66;H01L29/78;H01L21/8234;H01L27/088 主分类号 H01L21/70
代理机构 Muir Patent Law, PLLC 代理人 Muir Patent Law, PLLC
主权项 1. A semiconductor device, comprising a first gate pattern, a second gate pattern, and a third gate pattern disposed on an active region of a substrate, wherein the first gate pattern includes: a first gate insulating pattern formed on the active region of the substrate; a first gate dielectric pattern disposed on the first gate insulating pattern; a first gate barrier pattern disposed on the first gate dielectric pattern; a first metal layer including a first metal, the first metal layer disposed directly on the first gate barrier pattern; and a second metal layer including a second metal, the second metal layer disposed directly on the first metal layer, such that the first metal layer is between the first gate barrier pattern and the second metal layer, the second gate pattern includes: a second gate insulating pattern formed on the active region of the substrate; a second gate dielectric pattern disposed on the second gate insulating pattern; a second gate barrier pattern disposed on the second gate dielectric pattern; the second metal layer disposed directly on the second gate barrier pattern; and a third metal layer including a third metal, the third metal layer, disposed directly on the second metal layer, such that the second metal layer is between the second gate barrier pattern and the third metal layer, and the third gate pattern includes: a third gate insulating pattern formed on the active region of the substrate; a third gate dielectric pattern disposed on the third gate insulating pattern; a third gate barrier pattern disposed on the third gate dielectric pattern; the first metal layer disposed directly on the third gate barrier pattern; a fourth metal layer disposed directly on the first metal layer, such that the first metal layer is between the third gate barrier pattern and the fourth metal layer; and a fifth metal layer disposed directly on the fourth metal layer, such that the fourth metal layer is between the first metal layer and the fifth metal layer, wherein the sum of thicknesses of the first metal layer and the second metal layer of the first gate pattern is greater than a thickness of the second metal layer of the second gate pattern, and the sum of thicknesses of the first metal layer and the fourth metal layer of the third gate pattern is smaller than the thickness of the second metal layer of the second gate pattern.
地址 Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do KR