Phase frequency detector (PFD) circuit with improved lock time

摘要

Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.

主权项

1. A locking circuit to provide a clock output signal according to a reference clock signal, comprising:
a controlled oscillator including an output to provide an oscillator output clock signal according to a control voltage signal; a feedback circuit including a first output to provide a feedback clock signal according to the oscillator output clock signal; a loop filter circuit comprising an impedance and a second output to provide the control voltage signal according to a current signal; a charge pump circuit including a third output to generate the current signal according to a control input signal; and a phase frequency detector (PFD) circuit operative in a first mode to generate the control input signal having a pulse width corresponding to a phase difference between a reference clock signal and the feedback clock signal, and operative in a second mode to generate the control input signal with a constant value; and a mode control circuit operative to place the PFD circuit in the first mode when the phase difference between the reference clock signal and the feedback clock signal is less than a predetermined value, and operative in response to the phase difference exceeding the predetermined value to place the PFD circuit in the second mode for a predetermined time.