Organic light emitting display device

摘要

Discussed is an organic light emitting display device. The organic light emitting display device includes a first substrate configured to include an active area including a plurality of pixels and upper, lower, left, and right inactive areas defined near the active area, and a second substrate facing-coupled to the first substrate. The first substrate includes a plurality of data lines and a plurality of gate lines formed in the active area, a plurality of driving power lines formed in parallel with the plurality of data lines to supply a driving voltage to the pixels, a cathode electrode layer connected to the pixels in common to supply a cathode voltage to the pixels, a plurality of driving power pads provided in each of the upper and lower inactive areas, and a plurality of cathode connection parts provided in each of the left and right inactive areas.

主权项

1. An organic light emitting display device comprising:
a first substrate configured to comprise an active area comprising a plurality of pixels and upper, lower, left, and right inactive areas defined near the active area; a second substrate facing-coupled to the first substrate; a first data printed circuit board provided in an upper perimeter area outside of the first substrate; a second data printed circuit board provided in a lower perimeter area outside of the first substrate; a plurality of first data drivers provided between, and connected to, both the first data printed circuit board and the upper inactive area of the first substrate; and a plurality of second data drivers provided between, and connected to, both the second data printed circuit board and the lower inactive area of the first substrate, wherein the first substrate comprises:
a plurality of data lines and a plurality of gate lines formed in the active area to intersect each other, and configured to define a plurality of pixel areas in which the plurality of pixels are respectively formed;a plurality of driving power lines formed in the active area in parallel with the plurality of data lines, and configured to supply a driving voltage to the plurality of pixels;a cathode electrode layer connected to the plurality of pixels in common, and configured to supply a cathode voltage to the plurality of pixels;a plurality of driving power pads provided the upper inactive area, and a plurality of driving power pads provided in the lower inactive area;a first common driving power line formed in the upper inactive area, connected to an upper side of each of the plurality of driving power lines, and connected to the plurality of driving power pads provided in the upper inactive area;a second common driving power line formed in the lower inactive area, connected to a lower side of each of the plurality of driving power lines, and connected to the plurality of driving power pads provided in the lower inactive area; anda plurality of cathode connection parts provided in each of the left and right inactive areas to be connected to the cathode electrode layer,wherein the first data printed circuit board includes a first common driving power supply line connected to the plurality of first data drivers, and the second data printed circuit board includes a second common driving power supply line connected to the plurality of second data drivers,wherein each of the first data drivers is connected to two corresponding driving power pads of the plurality of driving power pads provided in the upper inactive area, each of the two corresponding driving power pads being disposed at opposite ends of a respective one of the first data drivers and each of the two corresponding driving power pads being connected to the first common driving power supply line,wherein each of the second data drivers is connected to two corresponding driving power pads of the plurality of driving power pads provided in the lower inactive area, each of the two corresponding driving power pads being disposed at opposite ends of a respective one of the second data drivers and each of the two corresponding driving power pads being connected to the second common driving power supply line,wherein the first common driving power line is connected to each of the plurality of first data drivers in the upper inactive area via the two corresponding driving power pads among the plurality of driving power pads provided in the upper inactive area, andwherein the second common driving power line is connected to each of the plurality of second data drivers in the lower inactive area via the two corresponding driving power pads among the plurality of driving power pads provided in the lower inactive area.