| 摘要 |
PURPOSE:To realize a PLL frequency synthesizer circuit capable of obtaining a signal whose oscillating frequency is maade constant even at frequency other than a multiple of N(frXN) of a reference frequency fr. CONSTITUTION:The PLL frequency synthesizer circuit is provided with a reference signal oscillator 21, a reference frequency divider 22, a frequency converter 23, a band pass filter(BPF) 24, a phase comparator (PD) 25, a loop filter(LPF) 26, a VCO(voltage controlled oscillator) 27, a frequency divider 28, comparison frequency dividers 29, 30 and a CPU 31, and a reference signal fr obtained by 1/R frequency division to a reference frequency fLCXO of the reference signal oscillator 21 is frequency-converted (fL1=fr+ or -fd/N) with a signal through the frequency divider 28 and the comparison frequency divider 29 to generate a reference signal and the phase of the reference signal and the phase of a comparison signal fr'(=fVCO/N) resulting from 1/N frequency division to a signal fVCO of the VCO 27 are compared. |
