发明名称 Method for validating simulating results of a system and equivalence comparison of digital circuits based on said method
摘要 The invention creates a technology for validating simulation results. The quickly growing number of components in modern complex systems often necessitates the introduction of abstractions, that render said systems manageable. However the abstractions, which often are based simplified assumptions, may impair the simulation results. The automatic post-processing method according to the invention safeguards the validity of the result. In most cases this can be reached, without restoring the complete description, which generally is too complex. The method, which is described for the validation of calculated counter-examples in an equivalence comparison of digital circuits can be used in all other applications, that allow for an analagous formalization of the abstraction step.
申请公布号 US2005043935(A1) 申请公布日期 2005.02.24
申请号 US20040488631 申请日期 2004.10.12
申请人 DRESCHSLER ROLF;GUNTHER WOLFGANG;STUBERT BURKHARD 发明人 DRESCHSLER ROLF;GUNTHER WOLFGANG;STUBERT BURKHARD
分类号 G05B17/02;G06F17/50;(IPC1-7):G06F17/50;G06G7/62 主分类号 G05B17/02
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