ABOVE MOTHERBOARD INTERPOSER WITH QUARTER WAVELENGTH ELECTRICAL PATHS

摘要

An apparatus includes a processor having an array of processor interconnects arranged to connect the processor to conductive paths, a circuit substrate having an array of circuit interconnects arranged to provide connections between the processor and the circuit substrate, the circuit substrate having conductive paths connected to the array of circuit interconnects, an interposer substrate arranged between the processor and the circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one processor interconnect in the array of interconnects on the processor, the conductive trace arranged at least partially parallel to the interposer substrate such that no electrical connection exists between the conductive trace in the interposer substrate and a corresponding one of the circuit interconnects on the circuit substrate, and at least one peripheral circuit connected to the at least one conductive trace

主权项

1. An apparatus comprising:
a processor having an array of processor interconnects arranged to connect the processor to conductive paths; a circuit substrate having an array of circuit interconnects arranged to provide connections between the processor and the circuit substrate, the circuit substrate having conductive paths connected to the array of circuit interconnects; an interposer substrate arranged between the processor and the circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one processor interconnect in the array of interconnects on the processor, the conductive trace arranged at least partially parallel to the interposer substrate such that no electrical connection exists between the conductive trace in the interposer substrate and a corresponding one of the circuit interconnects on the circuit substrate; and at least one peripheral circuit connected to the at least one conductive trace, wherein signals travel through the trace between the processor and the peripheral circuit in 100 picoseconds or less.