发明名称 Interface clock frequency switching using a computed insertion delay
摘要 An aspect includes a method of interface clock frequency switching control that includes determining a first clock delay adjustment of a clock signal for an interface at a first clock frequency. A controller determines a second clock delay adjustment for the interface operated at a second clock frequency. The controller computes an insertion delay between the clock signal and a data signal of the interface based on the first clock delay adjustment and frequency and the second clock delay adjustment and frequency. The controller also computes a third clock delay adjustment to operate the interface at a third clock frequency based on the insertion delay and a relative difference between the third clock frequency and the second clock frequency. The clock signal is adjusted based on the third clock delay adjustment to align timing of the clock signal with the data signal at the third clock frequency.
申请公布号 US9442512(B1) 申请公布日期 2016.09.13
申请号 US201514946993 申请日期 2015.11.20
申请人 International Business Machines Corporation 发明人 Coteus Paul W.;Dreps Daniel M.;Hunter Hillery C.;Kim Kyu-hyoun;Wiedemeier Glen A.
分类号 G06F1/00;G06F1/14 主分类号 G06F1/00
代理机构 Cantor Colburn LLP 代理人 Cantor Colburn LLP
主权项 1. A method of interface clock frequency switching control in a computer system, the method comprising: determining, by a controller, a first clock delay adjustment of a clock signal on a clock line of an interface of the computer system operated at a first clock frequency; changing the clock signal on the clock line from the first clock frequency to a second clock frequency; determining, by the controller, a second clock delay adjustment of the clock signal on the clock line of the interface operated at the second clock frequency; computing, by the controller, an insertion delay between the clock signal and a data signal of the interface based on the first clock delay adjustment, the first clock frequency, the second clock delay adjustment, and the second clock frequency; periodically updating the second clock delay adjustment and the insertion delay while operating the clock signal at the second clock frequency and prior to changing the clock signal from the second clock frequency to a third clock frequency; computing, by the controller, a third clock delay adjustment of the clock signal to operate the clock line of the interface at the third clock frequency based on the insertion delay and a relative difference between the third clock frequency and the second clock frequency; and adjusting the clock signal based on the third clock delay adjustment to align timing of the clock signal with the data signal at the third clock frequency.
地址 Armonk NY US