发明名称 Package module of battery protection circuit
摘要 Disclosed is a package module of a battery protection circuit. The package module comprises: a first internal connection terminal area and a second internal connection terminal area, and in which first and second internal connection terminals connected to a battery can provided with a bare cell are respectively disposed; an external connection terminal area, in which a plurality of external connection terminals are disposed; and a protection circuit area comprising a device area in which a plurality of passive devices forming the battery protection circuit are disposed and a chip area, which is adjacent to the device area, and in which a protection IC and a dual FET chip forming the battery protection circuit are disposed, are disposed between the external connection terminal area and the second internal connection terminal area.
申请公布号 US9450428(B2) 申请公布日期 2016.09.20
申请号 US201214351321 申请日期 2012.08.20
申请人 ITM SEMICONDUCTOR CO., LTD. 发明人 Na Hyeok-Hwi;Kim Young-Seok;Ahn Sang-Hoon;Park Sung-Beum;Park Seung-Wook;Cho Hyun-Mok;Park Sun-Bok;Park Jae-Goo;Hwang Ho-Suk
分类号 H02J7/00;H02H1/00;H02H3/08;H02H7/18;H01M10/42;H01M2/34;H01M10/0525;H01M2/02;H01M2/04 主分类号 H02J7/00
代理机构 Ladas & Parry LLP 代理人 Ladas & Parry LLP
主权项 1. A package module of a battery protection circuit, the package module comprising: first and second internal connection terminal areas individually disposed at two side edges of the package module and for respectively disposing first and second internal connection terminals to be connected to a battery can including a bare cell; an external connection terminal area adjacent to the first internal connection terminal area and for disposing a plurality of external connection terminals; and a protection circuit area comprising a device area for disposing a plurality of passive devices for forming the battery protection circuit, and a chip area adjacent to the device area and for disposing a protection integrated circuit (IC) and a dual field effect transistor (FET) chip for forming the battery protection circuit, and disposed between the external connection terminal area and the second internal connection terminal area, wherein the package module is packaged to expose the plurality of external connection terminals on an upper surface of the package module, and to expose the first and second internal connection terminals on a lower surface of the package module, wherein the dual FET chip comprising first and second FETs having a common drain, and the protection IC for controlling overdischarge and overcharge are stacked vertically or are disposed adjacent to each other on the chip area, and wherein the plurality of passive devices comprising at least one resistor and at least one capacitor are individually disposed to connect at least two of a plurality of conductive lines to each other on the device area, and wherein the package module has a lead frame structure comprising: a die pad disposed on the chip area and for mounting the protection IC and the dual FET chip; first through sixth passive device leads disposed on the device area so as to form the plurality of conductive lines; first through third external connection terminal leads disposed on the external connection terminal area so as to form the plurality of external connection terminals; a first internal connection terminal lead extending from the first external connection terminal lead from among the plurality of external connection terminal leads, and disposed on the first internal connection terminal area so as to form the first internal connection terminal; and a second internal connection terminal lead disposed on the second internal connection terminal area so as to form the second internal connection terminal.
地址 Chungbuk KR