发明名称 |
Integrated circuits and methods for fabricating integrated circuits with self-aligned vias |
摘要 |
Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line. |
申请公布号 |
US9520321(B2) |
申请公布日期 |
2016.12.13 |
申请号 |
US201514633914 |
申请日期 |
2015.02.27 |
申请人 |
GLOBALFOUNDRIES, INC. |
发明人 |
Ryan Errol Todd;Lin Sean X. |
分类号 |
H01L21/44;H01L29/40;H01L21/768;H01L23/522 |
主分类号 |
H01L21/44 |
代理机构 |
Lorenz & Kopf, LLP |
代理人 |
Lorenz & Kopf, LLP |
主权项 |
1. A method for fabricating an integrated circuit, the method comprising:
forming a first conductive interconnect line overlying a semiconductor substrate; after forming the first conductive interconnect line, forming an insulator cap defining a gap overlying the first conductive interconnect line; depositing an upper interlayer dielectric material over the insulator cap and in the gap over the first conductive interconnect line; etching a via through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line; and depositing a conductive material into the via to form a conductive via in contact with the first conductive interconnect line. |
地址 |
Grand Cayman KY |