CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY

摘要

PURPOSE:To accelerate access by reducing a load of a word line power source and accelerating the rise of a word line voltage. CONSTITUTION:This circuit is constituted of plural sectioned memory arrays (only M0 shown in figure), a main decoder for main word line MWL common for them, a division word line SWL for making a memory cell SL provided on the memory array an active state and a sub decoder 32A for selecting a specific division word line, and only the specific division word line SWL in the memory array MO is raised selectively by the main decoder and the sub decoder 32A. Since only the specific memory array is selected, the load for the main word line becomes 1/4 in the example, and the rise of word line potential becomes steep, and an access time is accelerated by that.