发明名称 |
Method for production of a memory cell arrangement |
摘要 |
A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).
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申请公布号 |
US6475866(B2) |
申请公布日期 |
2002.11.05 |
申请号 |
US20010774316 |
申请日期 |
2001.01.31 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
HOFMANN FRANZ;KRAUTSCHNEIDER WOLFGANG;WILLER JOSEF |
分类号 |
G11C11/56;H01L21/8246;H01L27/112;(IPC1-7):H01L21/336;H01L21/823;H01L29/76;H01L29/94 |
主分类号 |
G11C11/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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