| 摘要 |
<p>A clock and data recovery (=CDR) circuit (3) for detecting the bit phase of an incoming data signal (1) and generating an outgoing sampled data signal (9), comprising a phase detector and a local clock, wherein the outgoing sampled data signal (9) is generated by retiming the incoming data bits in the rhythm of the local clock, wherein the local clock is adjusted to the bit phase of the incoming data signal (1) detected by the phase detector, is characterized in that the phase detector comprises means for performing a short time cross correlation between the incoming data signal and the sampled data signal. This CDR circuit (3) can be operated at very high bit rates and with few adjustment efforts. <IMAGE></p> |
