| 摘要 |
A low voltage differential signal receiving device includes two differential receivers, two oversamplers, a phase locked loop, and a clock edge and data boundary detection & data extraction logic module. Clock and data signals are transmitted via channels having the same circuit layout, so that the clock signal is treated as another type of data signal. A frequency of sampling input clock and data is increased via asynchronous clock, clock transition is detected, and data bytes are extracted from clock and data samples. Therefore, the clock signal and the data signal have the same delay time to avoid any sampling error due to a difference in time sequence between the clock and the data. Meanwhile, due to the accurately increased sampling frequency, the sampled clock and the data signals are not adversely affected by different factors to enable upgraded data transmission efficiency and quality at the same time.
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