发明名称 |
Method for verifying function sequences of controller, involves forming development controller by controller in parallel manner, where controller has inlet and outlet, and development controller has finite state machine |
摘要 |
<p>The method involves forming a development controller (3) by a controller (2) in a parallel manner. The controller has at an inlet (2.1.1 to 2.1.n) and an outlet (2.2.1 to 2.2.m). The development controller has a finite state machine, which generates with technical specification or a specification. The function sequences of the controller are verified with the development controller on the basis of evaluation. An independent claim is also included for a device for verifying function sequences of a controller.</p> |
申请公布号 |
DE102007028721(A1) |
申请公布日期 |
2008.12.24 |
申请号 |
DE20071028721 |
申请日期 |
2007.06.21 |
申请人 |
IAV GMBH INGENIEURGESELLSCHAFT AUTO UND VERKEHR |
发明人 |
LAUER, JENS;NAKOINZ, MATTHIAS;ZSCHOPPE, RENE |
分类号 |
G05B23/02;G05B19/045 |
主分类号 |
G05B23/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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