Pulse signal output circuit and shift register

摘要

An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

主权项

1. A semiconductor device comprising:
a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor, wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor, wherein one of source and drain of the fourth transistor is electrically connected to a gate of the first transistor, wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor, wherein one of source and drain of the fifth transistor is electrically connected to a gate of the second transistor, wherein one of source and drain of the sixth transistor is electrically connected to the other of source and drain of the fifth transistor, wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the first transistor, wherein a first signal is input to the other of source and drain of the first transistor, wherein a first potential is input to the other of source and drain of the second transistor, and wherein a second signal is output from the one of source and drain of the first transistor.